HCTS4002MS Datasheet | Intersil

Features - 3 Micron Radiation Hardened CMOS SOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - LSTTL Input patibility - VIL = 0.8V Max - VIH = VCC/2 Min - Input Current Levels Ii ≤ 5µA at VOL, VOH NC 6 GND 7 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW Y1 A1 B1 C1 D1 NC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC Y2 D2 C2 B2 A2 NC Description The Intersil HCTS4002MS is a Radiation Hardened Dual 4-Input NOR Gate. A high on any input forces the output to a low state. The HCTS4002MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS4002MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Functional Diagram An Bn Yn Cn Ordering Information PART NUMBER HCTS4002DMSR TEMPERATURE RANGE -55o C to +125o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent PACKAGE 14 Lead SBDIP Dn TRUTH TABLE 14 Lead Ceramic Flatpack 14 Lead SBDIP INPUTS An L Bn L X H X X Cn L X X H X Dn L X X X H OUTPUTS Yn H L L L L HCTS4002KMSR -55o C to +125o C HCTS4002D/ Sample HCTS4002K/ Sample +25o C Sample +25o C Sample 14 Lead Ceramic Flatpack Die HCTS4002HMSR +25o C Die NOTE: L = Logic Level Low, H = Logic level High, X = Don’t...